1. Field of the Invention
The present invention relates to an apparatus and a method for transmitting/receiving a signal in a communication system, and more particularly to an apparatus and a method for transmitting/receiving a signal by using an Affine Permutation Matrix (APM)-Low Density Parity Check (LDPC) code, which is an improved structured LDPC code, in a communication system.
2. Description of the Related Art
Next-generation communication systems have evolved into the form of a packet service communication system for transmitting burst packet data to a plurality of Mobile Stations (MS), and the packet service communication system has been designed to be suitable for mass data transmission. Further, next-generation communication systems are actively considering using an LDPC code, together with a turbo code. The LDPC code is known to have an excellent performance gain at high-speed data transmission, and has an advantage in that it can enhance data transmission reliability by effectively correcting errors due to noise occurring in a transmission channel.
Reference will now be made to FIG. 1, which illustrates the structure of a signal transmission apparatus in a conventional communication system using an LDPC code.
Referring to FIG. 1, the signal transmission apparatus includes an encoder 111, a modulator 113 and a transmitter 115. First, if an information vector s to be transmitted occurs in the signal transmission apparatus, the information vector s is delivered to the encoder 111. The encoder 111 generates a codeword vector c, that is, a non-binary LDPC codeword, by encoding the information vector s in a predetermined encoding scheme, and then outputs the generated codeword vector c to the modulator 113. Here, the predetermined encoding scheme corresponds to a non-binary LDPC encoding scheme. The modulator 113 generates a modulation vector m by modulating the codeword vector c in a predetermined modulation scheme, and then outputs the generated modulation vector m to the transmitter 115. The transmitter 115 inputs therein the modulation vector m output from the modulator 113, executes transmission signal processing for the input modulation vector m, and then transmits the processed modulation vector m to a signal reception apparatus through an antenna.
Next, reference will be made to FIG. 2, which illustrates the structure of a signal reception apparatus in a conventional communication system using an LDPC code.
Referring to FIG. 2, the signal reception apparatus includes a receiver 211, a demodulator 213 and a decoder 215. First, a signal transmitted by a signal transmission apparatus, such as shown in FIG. 1, is received through an antenna of the signal reception apparatus, and the received signal is delivered to the receiver 211. The receiver 211 executes reception signal processing for the received signal to thereby generate a reception vector r, and then outputs the processed and generated reception vector r to the demodulator 213. The demodulator 213 inputs therein the reception vector r output from the receiver 211, generates a demodulation vector x by demodulating the input reception vector r in a demodulation scheme corresponding to a modulation scheme applied to a modulator of the signal transmission apparatus (that is, the modulator 113), and then outputs the generated demodulation vector x to the decoder 215. The decoder 215 inputs therein the demodulation vector x output from the demodulator 213, decodes the input demodulation vector x in a decoding scheme corresponding to an encoding scheme applied to an encoder of the signal transmission apparatus (that is, the encoder 111), and then outputs the decoded demodulation vector x into a finally restored information vector ŝ.
Meanwhile, the LDPC code has performance approximating a channel capacity limit presented in Shannon's channel coding theorem. In order to generate an LDPC code having such good performance, a cycle and a density distribution on the Tanner graph of an LDPC code must be considered, and particularly consideration must be given to maximizing a girth on the Tanner graph. Here, “girth” denotes a minimum cycle length on the Tanner graph of a parity check matrix of the LDPC code. The reason why consideration must be given to maximizing the girth on the Tanner graph is that a cycle on the Tanner graph must be generally longer in order not to cause performance deterioration, such as an error floor, which occurs when there are many comparatively short-length cycles (for example, cycles having a length of 4), on the Tanner graph.
Thus, research is being conducted to provide schemes for generating a parity check matrix in such a manner so as not to produce short-length cycles on the Tanner graph, two typical ones of which are Scheme 1, in which short-length cycles are removed from a given random LDPC code, and Scheme 2, in which an LDPC code with no short-length cycle is algebraically generated. Scheme 2 is mainly used from these two schemes because the memory capacity required for storing parity check matrixes is large, and it is difficult to implement efficient LDPC encoding in the case of Scheme 1. Here, an LDPC code generated by applying Scheme 2 is called a structured LDPC code, and reference will now be made to a parity check matrix of a general structured LDPC code, with reference to FIG. 3.
As illustrated in FIG. 3, the parity check matrix of a general structured LPDC code has a structure in which the overall parity check matrix is divided into a plurality of blocks, and a permutation matrix corresponds to each block. Here, it is assumed that the permutation matrix has a size of L×L. As seen from FIG. 3, the parity check matrix of the structured LDPC code is divided into (p×q) number of blocks, and a permutation matrix corresponds to each block. In FIG. 3, Papq indicates a permutation matrix located at an intersection point of a pth block row and a qth block column among the plurality of blocks. Here, the superscript “apq” is 0≦apq≦1 or apq=∞.
Further, the permutation matrix corresponding to each block is referred to as a “block matrix”. In the case where the respective block matrixes within the parity check matrix are selected to only an identity matrix, if the location of a non-zero element in the first row of each block matrix is determined, then the locations of the remaining non-zero elements, that is, (L−1) number of elements, are determined. Thus, the memory capacity required for storing information on the overall parity check matrix is reduced to 1/L, as compared with that in the case where the locations of non-zero elements irregularly distributed in each block matrix are selected, that is, in the case where an LDPC code is generated by applying Scheme 1.
It can be noted from the foregoing that the structured LDPC code has improved performance by considering not only the memory capacity required for storing parity check matrix information, but also efficient encoding. However, the structured LDPC code which is currently proposed in the art has a drawback in that its cycle is affected by a parent matrix thereof, and an upper limit is restricted by several numerals related to its parent matrix irrespective of which code length and permutation matrixes are selected.